In implementing or calculating a digital function in an electronic device or system, a predetermined number of bits may be used as the input for the function calculation. The greater the number of bits used as the input, the more accurate may be the output signal and the smaller the output error E; however, the complexity of the function calculation also increases with a greater number of input bits. If the number of input bits is reduced to reduce the complexity of the function calculation, the output error E will increase.
Implementing a digital function with a large number of input bits, such as a matrix inversion function or the like, requires complex calculation hardware and large memory capacity to deal with the large number of bits and can result in substantial consumption of current or power every time the function is performed or calculated. A software implementation of the digital function may also consume significant amounts of current or power in performing numerous instructions per second. Consumption of power may be critical in a battery operated digital device or system.
Accordingly, for the reason stated above, and for other reasons that will become apparent upon reading and understanding the present specification, there is a need for an apparatus and method that may use a reduced number of input bits without increasing the output error or quantization error, consume less power and permit the calculation hardware to be simpler and the memory capacity required to be smaller.